VHDL

Having defined the design requirements, you may be tempted to jump right into coding, but we suggest that you first decide upon a design methodology. By having an idea of how your design will be described, you will tend to write more efficient code that is realized, through synthesis, to the logic implementation you intended.

You’re probably already familiar with the methodologies top-down. Bottom up or flat. The first tow methods involve creating design hierarchies; the latter involves describing the circuit as a monolithic design.

The top down approach requires that you divide your design into functional components, each component having specific inputs and output and performing a particular function. A top level module is created to tie the design components together, as in a net list, and then the components themselves are designed. The bottom up approach involves just the opposite. Defining and designing the individual components, then bringing the pieces together to form the overall design. A flat designs is one in which the details of functional components are defined at the same level as the interconnecting of those functional components.

Flat designs work well for small designs, where having details of the underlying definition of a functional block does not distract from understanding the functionality of the chip-level design. For many of the smaller designs in this text, a flat approach is used. Hierarchical schemes prove useful in large designs in the text, a flat approach is used. Hierarchical shames prove useful in large designs consisting of multiple complex functional components. Levels of hierarchy can clarify the interconnection of components. Avoid using to many levels of hierarchy, however, because excessive levels make it difficult to understand the interconnection of design elements and the relevance to the overall design.

CODE THE DESIGN:- after deciding upon a design methodology, you can reference your block, dataflow, and state diagrams as you code your design, being careful of syntax and semantics. If you’re like many engineers, you will simply follow or edit an existing example to meet your particular needs. The key to writing good edit an existing example to meet your particular needs. The key to writing good VHDL code is to think in terms of hardware. More specific sally, think in terms of hardware. More specifically, think as the synthesis software “thinks” to understand how your design will be realized. A good portion of this book is devoted to helping you think like synthesis software so that you will write efficient code.

SIMULATE THE SOURCE CODE:-

For large designs, simulating the source code with a VHDL simulator will prove time-efficient. The process of concurrent engineering to the early rather than in series. Brings circuit simulation once a late stage task to the early stages of design, with source code simulation, flaws can be detected early in the design cycle, allowing you to make correction with the least possible impact to the schedule. For small designs, it is sometimes unnecessary or inefficient to simulate the source code. However, for larger designs, for which synthesis and place.